![]() A schematic of the circuit is shown in the figure. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. The input common- mode potential could lie between 0 and 10 V the output common- mode potential would be 2 V. As used here, " low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor ( CMOS) integrated circuits are designed to operate. Proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common- mode potential into (2) a pair of output signals having the same low differential potential and a low common- mode potential. High- Voltage-Input Level Translator Using Standard CMOS ![]() The functionality of the proposed circuit was verified using HSPICE with 0.35 μm 2P4M CMOS process technology. The circuit operates on a Â☐.6 V power supply and consumes 0.3 μW. The proposed design provides high dynamic range, controllable amplitude, high accuracy and is insensitive to temperature variations. The proposed design utilises one Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. A CMOS current-mode log(x) and log(1/x) functions generatorĪ novel Complementary Metal Oxide Semiconductor ( CMOS) current-mode low-voltage and low-power controllable logarithmic function circuit is presented.
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